Comments on: PuneChips: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL tricks for Design Engineers – 5 Nov

By: SystemVerilog and Designer Productivity | PuneTech

SystemVerilog and Designer Productivity | PuneTech — Wed, 18 Nov 2009 07:02:02 +0000

[...] PuneChips: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL tricks for Design Engin… (punetech.com) [...]

Chaitanya — Thu, 05 Nov 2009 18:05:27 +0000

Hi,
It was very well organized event. I like to extend my thanks to Aarti and Abhijit for organizing this event.

Thanks,
Chaitanya

Mon, 02 Nov 2009 05:01:43 +0000

[...] PuneChips: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL tricks for Design Engi… [...]