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Archive for the ‘asic’ tag.

Ajit Shelat, 1 Sept 2010

Pune based serial entrepreneur, Ajit Shelat, passed away yesterday (1st Sept 2010), in a car crash on the Bombay-Pune expressway.

PuneChips Editor’s Blog – SystemVerilog and Designer Productivity

As chip design complexity increases, designer productivity is failing to keep up. Industry must innovate and provide design tools that address this problem to survive and prosper.

CORRECTION: ASIC Verification – guest post by Arati Halbe

Yesterday’s PuneTech post, “ASIC Verification: Trends and Challenges” was actually a guest post by Arati Halbe. Due to an oversight, I forgot to include the “About the Author” section in the post (in fact, I forgot to include any mention of the fact that the post was by Arati.) I apologize for the oversight. Arati […]

ASIC Verification: Trends and Challenges

(This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune […]

PuneChips Event: ASIC Verification trends and challenges – Jagdish Doma, former director of VLSI design Conexant Systems – 20 Aug

Image via Wikipedia What: Trends and Challenges by Jagdish Doma, former director of VLSI design for Conexant Systems When: Thursday, 20th August, 6:30pm to 8:00pm Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation […]

India/China better markets today for tech startups – Ajit Shelat, SVP, Nevis Networks

The news of Nevis Networks’ death are a gross exaggeration. After a workforce reduction, and a change in strategy to focus on the India/China markets, Nevis is doing fine, and had their best quarter in 1Q2009.