Tag Archives: asic

Ajit Shelat, 1 Sept 2010

(Pune based serial entrepreneur, Ajit Shelat, passed away yesterday. This article and photo are by flickr user drona and are taken from this page. They’re reproduced here under the terms of the Creative Commons (BY-NC) license under which that page is published.)

Ajit Shelat

My friend Ajit Shelat passed away today. He was driving on the Mumbai-Pune Highway, and had an accident at about 530pm September 1, 2010.

He was a fellow alumnus and contemporary of IIT-Mumbai.

Trained entirely in India, he was perhaps the first Indian engineer who designed and developed a very complex LAN security chipset at Nevis Networks, entirely based out of Pune, India.

He was a co-founder of RIMO technologies, Switch-on Networks(with Moti Jiandani), and Nevis Networks. Switch-On Networks was sold to PMC-Sierra for $300M+.

He supported a wide variety of environmental causes and an avid hiker and naturalist. A prolific entrepreneur himself, he generously gave his time and money to his favorite causes: The environment, education and entrepreneurs.

Said Yatin Mundkur, a venture capitalist at Artiman Ventures, who used to work for Ajit at Godrej Industries, in the mid-eighties: “I am who I am today, because of Ajit. And a lot of us who reported to him at Godrej would gladly say that.”

I will fondly remember the many hikes I took with him, and particularly the many discussions I had with him during the early X Window System days.

He is survived by his wife Radha Shelat and daughter Arundhati, and mother and sister.


(Ajit Shelat was most recently the President and CEO of Nevis Networks, a company that he was trying to turn around after he and his partners had acquired the assets of the company from the previous investors. PuneTech had interviewed Ajit just before this. He is survived by his wife, Radha Shelat, (VP Engineering, and India MD of Librato, previously CTO of Symantec Pune & Veritas Pune), and daughter.)

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PuneChips Editor’s Blog – SystemVerilog and Designer Productivity

The most recent PuneChips event was easily the most successful one in the short history of the group. Over 50 engineers attended the “SystemVerilog” talk by Clifford Cummings, President of Sunburst Design and SystemVerilog industry guru. A big thank you to a few folks who made this possible is in order; first off Parag Mehta of Qlogic for connecting us with Cliff; secondly in addition to Parag, Pravin Desale and Deepak Lala of LSI, and Jagdish Doma of Virage Logic for driving the attendance. Last, but not the least, we must also thank Cliff for taking us through a complex topic in a very engaging manner. Cliff certainly held the audience in rapt attention through an hour of highly technical discussion. The Q&A session was also very engaging. Of course, Cliff being the industry celebrity that he is, was mobbed by engineers asking questions after his speech.

It is very clear that SystemVerilog is clearly targeted at improving designer productivity. Failing productivity due to increasing design complexity is one of the biggest challenges faced by chip designers today, and it is not at all surprising that the EDA tool industry is focused on rectifying this. The chart below (source: SEMATECH) shows a rather grim picture – while design complexity has been growing at 58% CAGR, productivity has been increasing at only 21% CAGR. It is obvious to anyone that tools that fill this gap will be in great demand.

Failing Designer Productivity (Source: SEMATECH)
Failing Designer Productivity (Source: SEMATECH)

The reason for increasing design complexity is multifold – decreasing geometries allow designers to add more and more elements to the chip, making the entire process challenging. Number of IP cores per chip has grown from ~30 in 2003 to over 250 in 2006 and possibly much more today (source: EETimes). In addition, a big bull’s eye has been painted on power consumption numbers and most chips now must be designed using low power techniques. Plus, increasing complexity means that chip verification becomes more complex; 50% of all ASIC designs today require respins due to functional/logic errors (Source: Colette International Research).

Rather than a single solution, it is very likely that a multitude of innovative solutions that address individual problems will emerge. For example, better modeling techniques that can give a very accurate QoR estimate at the architecture stage itself can reduce the design complexity downstream. Languages such as SystemVerilog literally reduce the lines of code that a designer or verification engineer must write, thus boosting productivity. Time also may be right for ESL design, which has been around for a while, as conventional techniques fail to keep up.

All in all, we live in very interesting times. Faster and smaller is not always for the better. The industry must innovate and rise up to the economic and design challenges if it is to survive and prosper.

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CORRECTION: ASIC Verification – guest post by Arati Halbe

Yesterday’s PuneTech post, “ASIC Verification: Trends and Challenges” was actually a guest post by Arati Halbe. Due to an oversight, I forgot to include the “About the Author” section in the post (in fact, I forgot to include any mention of the fact that the post was by Arati.) I apologize for the oversight.

Arati has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune and M.Tech from CEDT, Indian Institute of Science, Bangalore. See her linked-in profile for more details.

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ASIC Verification: Trends and Challenges

(This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune and M.Tech from CEDT, Indian Institute of Science, Bangalore. See Arati’s linked-in profile for more details.)

As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what.

The integrated circuit from an Intel 8742, a 8...
Click on the image to see all PuneChips articles on PuneTech. Image via Wikipedia

Keeping this in mind, PuneChips had verification expert Jagdish Doma talk about “ASIC verification: Trends and Challenges” on 20th August 2009. Though impacted by the H1N1 scare we had a small but diverse audience. Jagdish discussed in detail the strengths and limitations of the various techniques, viz: ESL, Formal verification, Dynamic simulation, FPGA prototyping and Emulation.

ESL or Electronic System Level testing is the newest trend. Supporters of ESL claim that it is a highly powerful system level modeling tool. It enables fast software bring-up if combined with an emulation/FPGA prototyping platform. ESL has been used successfully to validate systems for mobile applications where only one peripheral/application is active on the processor bus. ESL does not seem suitable for systems where multiple processes and interfaces are active simultaneously, like for example in a networking system.

Formal verification, a static verification technique which is mainly assertion based, is useful to check control paths. It cannot be used to verify datapaths. Dynamic simulation is a very effective way of verifying functionality of every block in the ASIC including the datapath. Gate level simulations performed after the back annotated placement and routing data is available are used to identify timing related issues or omissions/errors in stating multi-cycle paths.

The need to find hardware bugs as early as possible in the ASIC lifecycle drives the emulation and/or FPGA prototyping effort. Both these techniques enable the testing of scenarios which are generally not possible to test in dynamic functional verification, well before the actual silicon comes back from the fab. Emulation or prototyping also accelerate fast software ramp up and the software team can get a development platform ready well before the actual chip is available. Emulation involves running test cases on hardware accelerated platforms like Palladium from Cadence and Veloce from Mentor. For FPGA prototyping, Single or multiple FPGAs are used to build a PCB system targeted for the testing of the ASIC/SoC. The ASIC code is then fully or partially programmed on the FPGA/s and functionality can thus be tested.

Scenarios with much longer simulation times than what normal functional simulation allows can be run on the emulation platforms. All the internal signals are available for viewing and debug, just like in functional simulation. The FPGA prototype platform does enable longer test time, but the debugging available is limited. The hardware accelerators are costly, and investing in them makes sense if a company has lot of ASIC programs running simultaneously. For companies which have similar chips planned back to back, investing in a home grown FPGA based emulation/prototyping platform makes sense. Another advantage FPGA prototyping is that the RTL goes through a complete synthesis and place and route cycle and testing is done on a circuit which is as close to the real ASIC as possible.

To ensure that a bug free product reaches the customer is a complex activity and poses multiple challenges. Coverage, legacy code, repeatability are issues that need to be tackled. Ensuring that the coverage is at an acceptable level is important. Code coverage is run to find out if all the possibilities of a written code are exercised in a test suite. Simulators from cadence (ius), synopsys(vcs) and mentor (modelsim) have their own code coverage analyzers. Functional coverage means to find out if each feature listed in the specification for an ASIC/SoC is verified. It is essential that the functional specification document has an individual numbered paragraph for each feature so that traceability is easier. Functional coverage is an activity that needs planning, reviews and careful test case designing. Methodologies like eRM (e reuse methodology – Specman based) and OVM (open verification methodology – System verilog based) do assist checking functional coverage, but the inputs provided need careful specification and reviews.

Reviews, not just for coverage, but at every stage in the ASIC cycle are extremely important. One of the challenges encountered while designing an ASIC is that the hardware team interprets a certain behavior from software and the software expects that certain things are taken care of in hardware. It is very important to involve members from design team, verification team, architecture team, software & firmware team for verification review.

It takes a good amount of effort to come up with a verification environment, and it is very common for a team to use what has worked before when schedules are demanding. Legacy environment saves lot of time, but it also handicaps the team. Talking about saving time, efficiency goes a long way in shrinking the schedules. The initial time and effort investment in automation of repetitive tasks save lot of time in future. Use of re-usable methodologies will definitely save time and effort.

Finally, while choosing the verification flow for a certain ASIC, team needs to look at what is available in terms of resources as well as time, understand the end user requirement, and make a decision on which technique to employ at what stage.

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PuneChips Event: ASIC Verification trends and challenges – Jagdish Doma, former director of VLSI design Conexant Systems – 20 Aug

The integrated circuit from an Intel 8742, a 8...
Image via Wikipedia

What: Trends and Challenges by Jagdish Doma, former director of VLSI design for Conexant Systems
When: Thursday, 20th August, 6:30pm to 8:00pm
Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture Center on the right hand side. Map
Registration and fees: This event is free for all to attend. No registration required.

ASIC verification – Trends and Challenges

Jagdish will discuss the ASIC verification flow, various verification and validation techniques, and strength areas and limitations of each technique and the key challenges faced by companies during the ASIC verification cycle.

About the speaker – Jagdish Doma

Jagdish served as Director of VLSI Division for Conexant Systems in Pune where he was responsible for managing diverse teams involved in design, verification, validation, implementation, physical design and software development. During his 19 year career, Jagdish has held various senoir techical positions at Texas Instruments, Cirrus Logic and AMD. He brings a wide range of experience in Architecture, Design, pre-silicon verification, post-silicon validation and leading organizations to successful product development. Jagdish holds Bachelor’s in Electrical Engineering from University of Pune and a Master’s in Electrical Engineering fromTexas A&M University.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

PuneChips has been started by Abhijit Athavale, president and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at several companies. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

For more information, see the PuneTech wiki profile of PuneChips, and/or join the PuneChips mailing list.

Please forward this mail to anybody in Pune who is interested in semiconductors, chip design, VLSI design, chip testing, and embedded applications.

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India/China better markets today for tech startups – Ajit Shelat, SVP, Nevis Networks

Ajit Shelat Nevis Networks
Ajit Shelat, Senior Vice President of Engineering, Nevis Networks

Nevis Networks, a mostly-Pune-based-company (with “official” headquarters in the US, and an additional center in China), builds network switches and other network hardware that allows a company to secure it’s internal network from attacks and to enforce identity-based security policies. The company’s LANenforcer product family transparently protects the network from external malicious attacks, and also allows restricting access to different network resources based on users’ identities according to policies set by the system administrators. This can be customized to ensure different levels of access to different classes of users, employees, contractors, guests and other third parties. In addition, the product allows detailed reporting, auditing, employee activity reports that make it possible to analyze security breaches in very granular detail. And because it is hardware based, all of this is delivered in realtime with very low latency.

Nevis Networks’ customers range from financial services, healthcare, education and defense contractors and they deploy Nevis LANenforcers to protect sensitive network resources and assets, with an intention of reducing the overall costs and time to resolve security breaches and conduct network audits. The company is headquartered in Mountain View, CA, with additional R&D centers in Pune, India and Beijing, China.

The ongoing recession has hit Nevis Networks hard, and it downsized a very large fraction of its workforce late last year. On top of that, on Monday, in a report title “LSI Acquires Manpower Team of Navis Networking”, CXOToday implied that the company (which they alternately identified as Navis Networks or Nevis Networks in the article) had shutdown and the team taken over by LSI. Specifically, this is what CXOToday said:

With recession being an opportunity to invest for big MNCs, LSI Technologies, a provider of innovative silicon, systems and software technologies has acquired the team of Navis Networking based at Pune. With the R&D unit based out of Mountain View, California shutting down, LSI has acquired the manpower of the captive R&D centre in India.

After hearing from PuneTech readers that this report is misleading, we caught up with Ajit Shelat, Senior Vice President of Engineering for Nevis Networks, to learn that the reports of Nevis’ demise have been greatly exaggerated. Here is a quick report of the conversation we had with Ajit:

On the news that LSI has “acquired” the “manpower” of Nevis but not the company.

The report by CXOToday is misleading. What actually happened is much simpler. Due to the economic downturn last year, Nevis Networks was looking to downsize some of its workforce. A friendly interaction between the respective managements of Nevis and LSI led to movement of some of Nevis manpower to LSI. This was a simple case of Nevis ex-employees being hired by LSI en masse. It does not represent any sort of acquisition or even agreement between Nevis and LSI. And these are certainly not the entire team of Nevis Networks India, as implied by the CXOToday article.

In any case, Nevis networks is not shutting down. It continues to execute on a with strategy and focus.

On the current status of Nevis Networks

Nevis networks core team is still there and it is going strong. In fact, the last quarter was quite good and has been the best quarter for Nevis since the inception of the company.

What has happened is that due to the downturn, Nevis shifted its focus away from the US market to the India and China markets, reduced its workforce in the US and in India, and this new strategy appears to be working for them.

On the surprising fact that India/China are better markets than the US market

Since Nevis Networks is selling cutting edge technology, one would have expected US to be the logical market for these products. However, people really underestimate the extent of the effect the economic recession is having on the market there. While the markets really melted around September 2008, the signs have been obvious for at least an year before that, and starting Nov/Dec 2007, Nevis had started planning its strategy of shifting focus away from the US market to the India/China markets.

In tune with their new strategy, Nevis substantially reduced its India workforce. They continue to support existing customers in the US, but new customers are coming mainly from India – which is apparently not affected by the recession as much. In general, it is easier for a company with mainly Indian promoters to sell in India than in other countries.

China is another country where sales are expected to grow – Nevis is in the process of stengthening its sales presence in China. The Chinese market, having a significantly different character, takes a longer ramp up time to achieve its full potential – though a very good start has been made in terms of immediate sales. Like other markets, achieving full potential is really a function of getting the right people on the ground, and building the right relationships and customer confidence. All this effort is justified by the fact that the Chinese market has the potential to scale up dramatically.

More about Nevis Networks

Nevis Networks was founded in 2002 with the intention of building a network security solution with high speed and low latency, using its proprietary ASIC-based technology. As of last year, Nevis had raised a total of US$40 million in three rounds of funding from premier venture capital firms New Enterprise Associates, BlueRun Ventures (formerly Nokia Venture Partners) and New Path Ventures LLC. We are told that their funding situation has recently changed and an announcement to this effect is expected in the next couple of weeks.

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