Category Archives: punechips

Materials, mechanics, thermals, speed, power – Overview of Integrated Circuit Packaging – PuneChips 10th July

What: Overview of the field of electronics packaging – by Dr. Sandeep Sane, Intel Corp, (Ph.D. CalTech)
When: Saturday, 10 July, 10:30am to 12:30pm
Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture Center on the right hand side. Map
Registration and fees: This event is free for all to attend. No registration required.

PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips
PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips

Electronic Packaging – Materials and Mechanics Challenges

Electronic packaging has typically been defined as providing an enabling function and a space transformer between the IC feature sizes and the board & system level interconnects and over years it has grown to become a ubiquitous part of the overall electronic assembly. In certain market segments, such as flash memories, the package has evolved to become a key product differentiator and performance enabler. The scope of electronic packaging is very broad across multiple application areas such as CPUâs and Chipsets for the desktop, mobile and server segments, hand-held and wireless devices, telecom components & network processors, and memory devices; with each segment potentially having its unique set of demands and constraints such as the form factor, function, cost, reliability requirements, thermal and electrical performance.

To ensure that right technical and cost-effective solutions are defined, developed and deployed across the different market segments, electronic packaging provides significant research and development challenges and opportunities across multiple disciplines including materials, mechanics, reliability, thermals, high speed interconnects, power delivery and manufacturing.

This presentation will first provide an overview of current and future package technologies and associated demands in the different market segments, followed by focusing on some of the recent progress made in addressing some of the mechanics and materials challenges and highlight opportunities in future packaging technology development.

About the speaker – Dr. Sandeep Sane

Sandeep Sane received his Ph.D. from California Institute of Technology, Pasadena in Aerospace Engineering with major in Solid Mechanics. He holds M.S. in Aeronautics, California Institute of Technology and B.Tech in Mechanical Engineering from Indian Institute of Technology, Bombay (Mumbai).

Sandeep is currently a Technology Development manager in the Assembly and Test Technology Development (ATTD) organization, Intel Corp., Chandler. He manages a technical team of 30 engineers including an experimental mechanics laboratory; equipped with start of art analysis and validation metrologies. His team is chartered to deliver fundamental understanding of various mechanical issues in electronic packaging, establish roadmaps for ATTD and work directly with Intelâs customers (OEM/ODMs) and suppliers to resolve mechanical issues. He is also responsible for delivering novel mechanical analysis, material characterization and validation techniques to help optimize design, material and process changes to deliver reliable and cost effective solutions for Intelâs packaging technologies. Sandeep has led and participated in numerous taskforces and management review boards to resolve critical issues in a timely manner impacting Intelâs bottom-line. Prior to joining Intel, he was a Development Staff Engineer with IBM, Endicott, NY, working in Mechanical & Thermal Analysis group.

Sandeep has filed for more than 15 patents and have published several technical articles in various conferences and journal proceedings. He is also a recipient of numerous awards across Intel for his technical contributions. He is a member of ASME, IEEE and an active member of organizing committees for ASME and IEEE conferences. He also serves on Industrial Advisory Board for Mechanical Engineering at University of Colorado, Boulder and NSF review committee.

About Venture Center

Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

PuneChips has been started by Abhijit Athavale, president and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at several companies. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

For more information, see the PuneTech wiki profile of PuneChips, and/or join the PuneChips mailing list.

Please forward this mail to anybody in Pune who is interested in semiconductors, chip design, VLSI design, chip testing, and embedded applications.

Introducing http://PuneChips.com: The PuneTech SIG on Semiconductors, EDA, VLSI, Embedded Systems

Over the past 2 years, PuneTech has covered a breadth of technology related topics, with a concentration on Information Technology & Software. The strategic goal is to cover multiple technology segments and discuss innovative & exciting developments in these areas; specifically in Pune’s context.

It was with this objective that the concept of ‘SIG’ (Special Interest Group) was first mooted last year. A SIG covers a given vertical or horizontal domain area in depth. We decided that the best way to expand PuneTech would be to create a number of such SIGs, each focused on some particular vertical, and each run by someone who is passionate about that vertical. PuneTech would provide support, like a launching pad, publicity and visibility, and guidance about what works and what doesn’t work, based on our own experiences. Over time, we expect SIGs to have their own websites, and their own offline events.

PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips
PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips

PuneChips was the first SIG, launched in June of 2009, launched by Abhijit Athavale (SIG Leader) in cooperation with PuneTech. It focuses on semiconductors design and applications. This SIG has arranged many successful meetings and events, and now it has also launched has its own website: www.punechips.com . This website features information about the PuneChips events, as well as blogs about the semiconductors and embedded system industry. Volunteers like Arati Halbe have helped with PuneChips (but more volunteers are needed). Also, the Venture Center and Kaushik Gala have been helpful in graciously providing their premises for holding PuneChips events. For more details see the PuneChips about page.

PuneTech hopes to incubate more SIGs like PuneChips in future, and spin them off as separate entities. PuneTech will continue to be actively involved in supporting and publicizing the events and activities of these SIGs. If you’d like to start one, please get in touch with us.

PuneChips Activities

Over the past 8 months, PuneChips has organized a number of interesting meetings, featuring senior thought leaders from the semiconductor industry. It also has an active google-groups mailing list and a ‘Pune Chips’ linkedin group. Nearly 200 professionals and students from the VLSI, Embedded Systems, and other related areas are members of these groups. You can also follow PuneChips on twitter.

The first kick-off meeting of PuneChips in June 2009 featured Abhijit Abhyankar, Head of Rambus India. His talk on Emerging opportunities in the semiconductor industry presented a nice overview of the semiconductor sector and its progression over the past few decades. He also discussed emerging opportunities and trends in this field.

The second event featured Shrinath Keskar, ex-MD of Ikanos India. His presentation: IC Design Challenges in the Telecom sector discussed the various challenges in IC Design, specifically with respect to the Telecom Sector.

The August 2009 speaker Jagdish Doma, former director of VLSI design Conexant Systems, covered ASIC Verification trends and challenges.

The October 2009 session featured a talk by Cliff Cummings, President of Sunburst Design and SystemVerilog Industry Guru. He talked about SystemVerilog & Designer Productivity, discussing specific tools and tricks for improving designer productivity.

The January session featured Madhu Atre, President of Applied Materials India. His talk on A Bright Solar Future discussed the various new developments in the area of solar power (specifically photo-voltaic) and the macro alternate energy global trends. He also touched upon the implications of these developments for India, including costs and government incentives.

In 2010, PuneChips plans to arrange similar meetings, featuring talks by thought leaders from the industry. The SIG also looks forward to more active interactions on the mailing list and linkedin group. If you are interested in learning more about the PuneChips activities and/or have a speaker you would like to recommend, please contact Abhijit Athavale.

You should form a SIG too – Get in touch with us

It would be great if Pune has many more such SIGs. A number of such groups and organizations are already active (some like the Pune Linux Users Group have existed long before PuneTech was started, and most like the Pune Open Coffee Club, for entrepreneurs and startups, were created independently). But there is scope for many more. The existing ones largely tend to be focused on particular technologies (like the Google Technologies User Group, or the Pune User Group for Microsoft Technologies). There are only a few that are aligned with industry verticals, like PuneChips or the Null group focused on security. I think there should be more.
So, if you’re passionate about some industry vertical, and are willing to spend at least a few hours a week on organizing a Pune-based SIG around that vertical, and are willing to do that for at least a couple of years, please let in touch with us, and let us make it happen.

In fact, it does not even have to be a vertical. It can be a horizontal area that goes across groups. As long as it is something that benefits Pune’s techies, we are game. In fact, we’re soon expecting to make an announcement related to PuneTech and Marathi. Subscribe to PuneTech so you don’t miss it.

PuneChips event: Wavelet Transform & its Applications in Image Processing – 6th March

(This article about a PuneChips event is reproduced with permission from the PuneChips website)

What: Talk by Ganesh Bhokare on Wavelet Transform & its Applications in Image Processing
When
: Saturday, 6th March 2010, 10:00 am to 12:00 noon.
Where: Venture Center, NCL Innovation Park, Pashan Road
Registration and fees: This event is *FREE* for all to attend. No registration required.

PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the image to see all PuneTech articles about PuneChips
An image of a two level wavelet transform. A PuneChips event, on the Wavelet Transform and its applications in Image Processing will be held in Venture Center on 6th March. PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips. Image by Alessio Damato via Wikipedia.

Wavelet Transform & its Applications in Image Processing

In today’s multimedia wireless communication , major issue is bandwidth needed to satisfy real time transmission of audio and video data. The solution to this problem is to efficiently compress audio and video data for a given SNR. Wavelet transform is an evolving technology which offers far higher degrees of data compression compared to standard transforms such as DCT etc. In this talk we will be discussing concepts of wavelet transform and its applications to image compression and processing. The same can be extended to video processing.

About the speaker – Ganesh Bhokare

Ganesh Bhokare has over 15 years experience in using DSP audio, video and Embedded systems for Digital Media Processing. He is a PhD candidate at IIT Mumbai and currently in the process of defending his thesis. He has professional experience with  NXP, Conexant, TI and Cirrus Logic.

About Venture Center

Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

For more information, see the PuneChips website at http://punechips.com, and/or join the PuneChips mailing list: http://groups.google.com/group/punechips.  Please forward this mail to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

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PuneChips talk: A Bright Solar Future, by Madhu Atre, President Applied Materials India – 16 Jan

What: Talk about Solar Energy, by Madhu Atre, President of Applied Materials India
When: Saturday, 16 January, 10am to 12noon
Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture Center on the right hand side. Map
Registration and fees: This event is free for all to attend. No registration required.

PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips
PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips

India – A Bright Solar Future

As global warming begins showing its bad side, it is important for everyone to harvest new and renewable sources of energy. Applied Material is and continues to be a pioneer in the field of solar energy. Madhu will talk about trends in solar technologies, viability, opportunities (especially software/services related) from an India perspective

About the speaker – Dr. Madhu Atre

Dr. Madhusudan V. Atre (Madhu) is the President & Managing Director of Applied Materials India. As the leader of the Applied Materials India management team, he is responsible for strategy and operations in India; and ensures alignment, coordination and execution of all product development, business, and operational activities. Dr. Atre represents Applied Materials in India to the employees, customers, business partners, local and central government officials. He also provides executive leadership at all the India sites, and is the Applied Materials India legal representative. With over 24 years of experience in the semiconductor and computer industries after his PhD, Dr. Atre has also donned other technical, management and leadership roles â as the Vice President and Managing Director of LSI India, founding Managing Director and Vice President of Agere Systems India, founding director of Lucent Technologies Microelectronics Division, and several management positions at Texas Instruments India, and Indiaâs Defence R&D Organization

Dr. Atre has published/authored more than 40 technical papers/articles in reputed journals/conferences, as well as thought leadership articles on semiconductor and solar industry; and also lectured in many technical and industry forums. He holds a 5 year integrated M.Sc. degree in physics from the Indian Institute of Technology (IIT) Bombay, and a Ph.D. in theoretical physics from the Indian Institute of Science (IISc) Bangalore. He has been a research scientist at the Tata Institute of Fundamental Research (Mumbai), Physical Research Laboratory (Ahmedabad), and universities in the US and Italy.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

PuneChips has been started by Abhijit Athavale, president and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at several companies. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

For more information, see the PuneTech wiki profile of PuneChips, and/or join the PuneChips mailing list.

Please forward this mail to anybody in Pune who is interested in semiconductors, chip design, VLSI design, chip testing, and embedded applications.

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PuneChips Editor’s Blog – SystemVerilog and Designer Productivity

The most recent PuneChips event was easily the most successful one in the short history of the group. Over 50 engineers attended the “SystemVerilog” talk by Clifford Cummings, President of Sunburst Design and SystemVerilog industry guru. A big thank you to a few folks who made this possible is in order; first off Parag Mehta of Qlogic for connecting us with Cliff; secondly in addition to Parag, Pravin Desale and Deepak Lala of LSI, and Jagdish Doma of Virage Logic for driving the attendance. Last, but not the least, we must also thank Cliff for taking us through a complex topic in a very engaging manner. Cliff certainly held the audience in rapt attention through an hour of highly technical discussion. The Q&A session was also very engaging. Of course, Cliff being the industry celebrity that he is, was mobbed by engineers asking questions after his speech.

It is very clear that SystemVerilog is clearly targeted at improving designer productivity. Failing productivity due to increasing design complexity is one of the biggest challenges faced by chip designers today, and it is not at all surprising that the EDA tool industry is focused on rectifying this. The chart below (source: SEMATECH) shows a rather grim picture – while design complexity has been growing at 58% CAGR, productivity has been increasing at only 21% CAGR. It is obvious to anyone that tools that fill this gap will be in great demand.

Failing Designer Productivity (Source: SEMATECH)
Failing Designer Productivity (Source: SEMATECH)

The reason for increasing design complexity is multifold – decreasing geometries allow designers to add more and more elements to the chip, making the entire process challenging. Number of IP cores per chip has grown from ~30 in 2003 to over 250 in 2006 and possibly much more today (source: EETimes). In addition, a big bull’s eye has been painted on power consumption numbers and most chips now must be designed using low power techniques. Plus, increasing complexity means that chip verification becomes more complex; 50% of all ASIC designs today require respins due to functional/logic errors (Source: Colette International Research).

Rather than a single solution, it is very likely that a multitude of innovative solutions that address individual problems will emerge. For example, better modeling techniques that can give a very accurate QoR estimate at the architecture stage itself can reduce the design complexity downstream. Languages such as SystemVerilog literally reduce the lines of code that a designer or verification engineer must write, thus boosting productivity. Time also may be right for ESL design, which has been around for a while, as conventional techniques fail to keep up.

All in all, we live in very interesting times. Faster and smaller is not always for the better. The industry must innovate and rise up to the economic and design challenges if it is to survive and prosper.

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PuneChips: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL tricks for Design Engineers – 5 Nov

What: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL Tricks for Design Engineers
When: Thursday, 5th November, 6:30pm to 8:00pm
Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture Center on the right hand side. Map
Registration and fees: This event is free for all to attend. No registration required.

The integrated circuit from an Intel 8742, a 8...
Click on the image to see all PuneTech articles about PuneChips. Image via Wikipedia

SystemVerilog FSM, Assertion, & RTL Tricks for Design Engineers

In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. As companies start migrating from Verilog to SystemVerilog it is becoming importatnt that they learn the tools of tread to effectively use it.

About the speaker – Cliff Cummings

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world class Verilog, SystemVerilog and synthesis training. Mr. Cummings is an independent consultant and trainer with 27 years of ASIC, FPGA and system design experience and 17 years of Verilog, SystemVerilog, synthesis and methodology training experience. Mr. Cummings has completed many ASIC designs, FPGA designs and system simulation projects, and is capable of answering the very technical questions asked by experienced design engineers.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

PuneChips has been started by Abhijit Athavale, president and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at several companies. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

For more information, see the PuneTech wiki profile of PuneChips, and/or join the PuneChips mailing list.

Please forward this mail to anybody in Pune who is interested in semiconductors, chip design, VLSI design, chip testing, and embedded applications.

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CORRECTION: ASIC Verification – guest post by Arati Halbe

Yesterday’s PuneTech post, “ASIC Verification: Trends and Challenges” was actually a guest post by Arati Halbe. Due to an oversight, I forgot to include the “About the Author” section in the post (in fact, I forgot to include any mention of the fact that the post was by Arati.) I apologize for the oversight.

Arati has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune and M.Tech from CEDT, Indian Institute of Science, Bangalore. See her linked-in profile for more details.

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ASIC Verification: Trends and Challenges

(This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune and M.Tech from CEDT, Indian Institute of Science, Bangalore. See Arati’s linked-in profile for more details.)

As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what.

The integrated circuit from an Intel 8742, a 8...
Click on the image to see all PuneChips articles on PuneTech. Image via Wikipedia

Keeping this in mind, PuneChips had verification expert Jagdish Doma talk about “ASIC verification: Trends and Challenges” on 20th August 2009. Though impacted by the H1N1 scare we had a small but diverse audience. Jagdish discussed in detail the strengths and limitations of the various techniques, viz: ESL, Formal verification, Dynamic simulation, FPGA prototyping and Emulation.

ESL or Electronic System Level testing is the newest trend. Supporters of ESL claim that it is a highly powerful system level modeling tool. It enables fast software bring-up if combined with an emulation/FPGA prototyping platform. ESL has been used successfully to validate systems for mobile applications where only one peripheral/application is active on the processor bus. ESL does not seem suitable for systems where multiple processes and interfaces are active simultaneously, like for example in a networking system.

Formal verification, a static verification technique which is mainly assertion based, is useful to check control paths. It cannot be used to verify datapaths. Dynamic simulation is a very effective way of verifying functionality of every block in the ASIC including the datapath. Gate level simulations performed after the back annotated placement and routing data is available are used to identify timing related issues or omissions/errors in stating multi-cycle paths.

The need to find hardware bugs as early as possible in the ASIC lifecycle drives the emulation and/or FPGA prototyping effort. Both these techniques enable the testing of scenarios which are generally not possible to test in dynamic functional verification, well before the actual silicon comes back from the fab. Emulation or prototyping also accelerate fast software ramp up and the software team can get a development platform ready well before the actual chip is available. Emulation involves running test cases on hardware accelerated platforms like Palladium from Cadence and Veloce from Mentor. For FPGA prototyping, Single or multiple FPGAs are used to build a PCB system targeted for the testing of the ASIC/SoC. The ASIC code is then fully or partially programmed on the FPGA/s and functionality can thus be tested.

Scenarios with much longer simulation times than what normal functional simulation allows can be run on the emulation platforms. All the internal signals are available for viewing and debug, just like in functional simulation. The FPGA prototype platform does enable longer test time, but the debugging available is limited. The hardware accelerators are costly, and investing in them makes sense if a company has lot of ASIC programs running simultaneously. For companies which have similar chips planned back to back, investing in a home grown FPGA based emulation/prototyping platform makes sense. Another advantage FPGA prototyping is that the RTL goes through a complete synthesis and place and route cycle and testing is done on a circuit which is as close to the real ASIC as possible.

To ensure that a bug free product reaches the customer is a complex activity and poses multiple challenges. Coverage, legacy code, repeatability are issues that need to be tackled. Ensuring that the coverage is at an acceptable level is important. Code coverage is run to find out if all the possibilities of a written code are exercised in a test suite. Simulators from cadence (ius), synopsys(vcs) and mentor (modelsim) have their own code coverage analyzers. Functional coverage means to find out if each feature listed in the specification for an ASIC/SoC is verified. It is essential that the functional specification document has an individual numbered paragraph for each feature so that traceability is easier. Functional coverage is an activity that needs planning, reviews and careful test case designing. Methodologies like eRM (e reuse methodology – Specman based) and OVM (open verification methodology – System verilog based) do assist checking functional coverage, but the inputs provided need careful specification and reviews.

Reviews, not just for coverage, but at every stage in the ASIC cycle are extremely important. One of the challenges encountered while designing an ASIC is that the hardware team interprets a certain behavior from software and the software expects that certain things are taken care of in hardware. It is very important to involve members from design team, verification team, architecture team, software & firmware team for verification review.

It takes a good amount of effort to come up with a verification environment, and it is very common for a team to use what has worked before when schedules are demanding. Legacy environment saves lot of time, but it also handicaps the team. Talking about saving time, efficiency goes a long way in shrinking the schedules. The initial time and effort investment in automation of repetitive tasks save lot of time in future. Use of re-usable methodologies will definitely save time and effort.

Finally, while choosing the verification flow for a certain ASIC, team needs to look at what is available in terms of resources as well as time, understand the end user requirement, and make a decision on which technique to employ at what stage.

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PuneChips Event: ASIC Verification trends and challenges – Jagdish Doma, former director of VLSI design Conexant Systems – 20 Aug

The integrated circuit from an Intel 8742, a 8...
Image via Wikipedia

What: Trends and Challenges by Jagdish Doma, former director of VLSI design for Conexant Systems
When: Thursday, 20th August, 6:30pm to 8:00pm
Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture Center on the right hand side. Map
Registration and fees: This event is free for all to attend. No registration required.

ASIC verification – Trends and Challenges

Jagdish will discuss the ASIC verification flow, various verification and validation techniques, and strength areas and limitations of each technique and the key challenges faced by companies during the ASIC verification cycle.

About the speaker – Jagdish Doma

Jagdish served as Director of VLSI Division for Conexant Systems in Pune where he was responsible for managing diverse teams involved in design, verification, validation, implementation, physical design and software development. During his 19 year career, Jagdish has held various senoir techical positions at Texas Instruments, Cirrus Logic and AMD. He brings a wide range of experience in Architecture, Design, pre-silicon verification, post-silicon validation and leading organizations to successful product development. Jagdish holds Bachelor’s in Electrical Engineering from University of Pune and a Master’s in Electrical Engineering fromTexas A&M University.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

PuneChips has been started by Abhijit Athavale, president and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at several companies. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

For more information, see the PuneTech wiki profile of PuneChips, and/or join the PuneChips mailing list.

Please forward this mail to anybody in Pune who is interested in semiconductors, chip design, VLSI design, chip testing, and embedded applications.

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Too Soon to call for a Semiconductor Recovery?

(This post by Abhijit Athavale, the driving force behind PuneTech’s PuneChips forum, is cross-posted from his blog.)

Are we really out of the most dreaded recession after the great depression and on our path to recovery? The answer might be a resounding yes if we look at the recent crop of earnings reports from technology companies, and other data emerging from market analysis firms. In fact, the NASDAQ composite is already into deeply positive territory on the expectations of an imminent recovery.

Revenue and Inventory Declines from 2008 to 2009
Revenue and Inventory Declines from 2008 to 2009

However, a quick dissection of recent earnings announcements from a few prominent semiconductor companies shows that we are not out of the woods yet. The chart above shows that sales numbers are still horribly bad compared to last year, and inventories have declined sharply as well. This means that companies have managed to satisfy the underlying demand by using up their inventories, and will or already have started ordering replacement units from fabs. This explains why the fabs have reported better numbers than the IC vendors. In a normal growth phase, every company wants to keep its channel well stocked to feed demand. This is not the case now as companies are drawing down on finished stock to reduce costs and improve margins. So much for the expected recovery in demand …

Where does this demand come from ultimately? The consumer, of course. The US, Europe (as a whole) and Japan are the three largest economies in the world.

People living in these countries constantly keep (or, at least used to) buying new things such as laptops and PCs, cell phones, gaming consoles, automobiles, audio and video equipment, personal media players, TVs, toys, and other gadgets. Companies that manufacture consumer electronics ICs directly feed this demand. Consumers also buy services such as wireless and wireline voice and data, broadband, cable and satellite TV feeds. This in turn generates demand for the entire telecom, datacom and wireless infrastucture and service providers. Infrastructure IC manufacturers are responsible for suppplying this demand. In the US alone, the consumer is 70% of the entire economy. The consumer is also a major portion of the EU and Japanese economies. The consumption in all three major economies in the world has cratered, as evidenced by the continuous 6 to 9 month declines in the exports from China, Taiwan and Japan, major export reliant countries.

The real demand will not be back till the consumer starts spending again. And, that is almost impossible in this economy. Take the US for example – official unemployment is at ~11% (some say, it is near 16% unofficially), one in ten homeowners is underwater, and credit lines have been severely downgraded by banks. Three major sources of funds used by consumers have been seriously compromised. To use a banking term, the consumer is now de-leveraging and getting his house in order. There will be no more spending sprees till the US savings rates are back to historical levels. The EU and Japan are in even worse situations as their banks are still over leveraged and that still needs to be played out a la Bear Sterns and Lehman Brothers.

My belief is that the semiconductor industry and the companies that serve the semiconductor industry are not coming back till personal finances get better. That is not likely to happen for a while. Some analysts are calling Q2, 2009 as the bottom, which very well may be so, but I don’t expect to see a quick recovery from this point on. In fact, the worsening unemployment and foreclosure numbers may push us back into a double dip recession. If not, the recovery will be tepid and totally unspectacular.

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