Tag Archives: punechips

Opinion: Pune’s IT industry must focus on electronic design (ESDM) – Gouri Agtey Athale

Technology, , , , ,

Gouri Agtey Athale has an interesting article in the Pune Mirror pointing out that following the success of the “animation and gaming” niche sector, the IT industry in Pune should start focusing on other niche sectors – for example electronic design.

Excerpts:

[The] niche area of animation and gaming has worked out for Pune the way the software industry worked on the existing industrial base: combining the existing dormant and untapped potential and build a whole new business out of it.

Pune’s arrival on the animation and gaming scene has received recognition at the international level: two animation films made by companies based in Pune have made it to the list of Oscar nominations, Krayon’s Delhi Safari and Reliance Big’s Krishna and Kaunsa.

and

That was in the past: the move now is to move on and the next wave could be a convergence of the hardware and software sectors to create ESDM, or Electronic System Design and Manufacturing. Cmde (retd) Anand Khandekar, former member of the IT committee of the MCCIA, who helped draft the state’s IT policy over a decade ago, suggested that existing expertise in embedded software and the presence of the hardware sector in the city could be married to the city’s industrial culture and the educational base to create an industry around ESDM.

The blue print that ESDM is looking at is that of the automotive sector, where there are vendors who supply to the original equipment manufacturer, the OEM. On these lines, local entities could become vendors to global companies, the example usually cited being that of Taiwanbased companies who work on projects for global majors like Apple, Oracle-Sun Micro and Google- Motorola.

and finally:

And the sector needs a champion, a strong, non-partisan platform, which in the case of Pune’s software industry was the MCCIA.

Read the full article

Event Report: VLSI Design Conference Pune 2013

Event Report, In Depth, , , ,
(This is an event report of the VLSI Design Conference that was held in Pune in Jan 2013, by Shakthi Kannan. It originally appeared on his blog, and is reproduced here with permission for the benefit of PuneTech readers.)

The 26th International Conference on VLSI Design 2013 and the 12th International Conference on Embedded Systems was held at the Hyatt Regency, Pune, India between January 5-10, 2013. The first two days were tutorial sessions, while the main conference began on Monday, January 7, 2013.

26th VLSID 2013

Day 1: Tutorial

On the first day, I attended the tutorial on “Concept to Product – Design, Verification & Test: A Tutorial” by Prof. Kewal Saluja, and Prof. Virendra Singh. Prof. Saluja started the tutorial with an introduction and history of VLSI. An overview of the VLSI realization process was given with an emphasis on synthesis. The theme of the conference was “green” technology, and hence the concepts of low power design were introduced. The challenges of multi-core and high performance design including cache coherence were elaborated. Prof. Singh explained the verification methodologies with an example of implementing a DVD player. Simulation and formal verification techniques were compared, with an overview on model checking. Prof. Saluja explained the basics of VLSI testing, differences between verification and testing, and the various testing techniques used. The challenges in VLSI testing were also discussed.

Day 2: Tutorial

On the second day, I attended the tutorial on “Formal Techniques for Hardware/Software Co-Verification” by Prof. Daniel Kroening, and Prof. Mandayam Srinivas. Prof. Kroening began the tutorial with the motivation for formal methods. Examples on SAT solvers, boundary model checking for hardware, and bounded program analysis for C programs were explained. Satisfiability modulo theories for bit-vectors, arrays and functions were illustrated with numerous examples. In the afternoon, Prof. Srinivas demoed formal verification for both Verilog and C. He shared the results of verification done for both a DSP and a microprocessor. The CProver tool has been released under a CMBC license. After discussion with Fedora Legal, and Prof. Kroening, it has been updated to a BSD license for inclusion in Fedora. The presentation slides used in the tutorial are available.

Day 3: Main conference

The first day of the main conference began with the keynote by Mr. Abhi Talwalker, CEO of LSI, on “Intelligent Silicon in the Data-centric Era”. He addressed the challenges in bridging the data deluge gap, latency issues in data centers, and energy efficient buildings. The second keynote of the day was given by Dr. Ruchir Puri, IBM Fellow, on “Opportunities and Challenges for High Performance Microprocessor Designs and Design Automation”. Dr. Ruchir spoke about the various IBM multi-core processors, and the challenges facing multi-core designs – software parallelism, socket bandwidth, power, and technology complexity. He also said that more EDA innovation needs to come at the system level.

Dias

After the keynote, I attended the “C1. Embedded Architecture” track sessions. Liang Tang presented his paper on “Processor for Reconfigurable Baseband Modulation Mapping”. Dr. Swarnalatha Radhakrishnan then presented her paper on “A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-Set Processors”. She explained about ASIPs (Application Specific Instruction Set Processor), and shared test results on choosing specific instruction sets based on the application domain. The final paper for the session was presented by Prof. Niraj K. Jha on “Localized Heating for Building Energy Efficiency”. He and his team at Princeton have used ultrasonic sensors to implement localized heating. A similar approach is planned for lighting as well.

Post-lunch, I attended the sessions for the track “B2. Test Cost Reduction and Safety”. The honourable chief minister of Maharashtra, Shri. Prithviraj Chavan, arrived in the afternoon to formally inaugurate the conference. He is an engineer who graduated from the University of California, Berkeley, and said that he was committed to put Pune on the semiconductor map. The afternoon keynote was given by Mr. Kishore Manghnani from Marvell, on “Semiconductors in Smart Energy Products”. He primarily discussed about LEDs, and their applications. This was followed by a panel discussion on “Low power design”. There was an emphasis to create system level, software architecture techniques to increase leverage in low power design. For the last track of the day, I attended the sessions on “C3. Design and Synthesis of Reversible Logic”. The Keccak sponge function family has been chosen to become the SHA-3 standard.

Day 4: Main conference

The second day of the main conference began with a recorded keynote by Dr. Paramesh Gopi, AppliedMicro, on “Cloud computing needs at less power and low cost” followed by a talk by Mr. Amal Bommireddy, AppliedMicro, on “Challenges of First pass Silicon”. Mr. Bommireddy discussed the factors affecting first pass success – RTL verification, IP verification, physical design, routing strategies, package design, and validation board design. The second keynote of the day was by Dr. Louis Scheffer from the Howard Hughes Medical Institute, on “Deciphering the brain, cousin to the chip”. It was a brilliant talk on applying chip debugging techniques to inspect and analyse how the brain works.

After the keynote, I visited the exhibition hall where companies had their products displayed in their respective stalls. AppliedMicro had a demo of their X-gene ARM64 platform running Ubuntu. They did mention to me that Fedora runs on their platform. Marvell had demonstrated their embedded and control solutions running on Fedora. ARM had their mbed.org and embeddedacademic.com kits on display for students. Post-lunch, was an excellent keynote by Dr. Vivek Singh, Intel Fellow, titled “Duniyaa Maange Moore!”. He started with what people need – access, connectivity, education, and healthcare, and went to discuss the next in line for Intel’s manufacturing process. The 14nm technology is scheduled to be operational by end of 2013, while 10nm is planned for 2015. They have also started work on 7nm manufacturing processes. This was followed by a panel discussion on “Expectations of Manufacturing Sector from Semiconductor and Embedded System Companies” where the need to bridge the knowledge gap between mechanical and VLSI/embedded engineers was emphasized.

Day 5: Main conference

The final day of the main conference began with the keynote by Dr. Vijaykrishnan Narayanan on “Embedded Vision Systems”, where he showed the current research in intelligent cameras, augmented reality, and interactive systems. I attended the sessions for the track “C7. Advances in Functional Verification”, and “C8. Logic Synthesis and Design”. Post-lunch, Dr. Ken Chang gave his keynote on “Advancing High Performance System-on-Package via Heterogeneous 3-D Integration”. He said that Intel’s 22nm Ivy Bridge which uses FinFETs took nearly 15 years to productize, but look promising for the future. Co(CoS) Chip on Chip on Substrate, and (CoW)oS Chip on Wafer on Substrate technologies were illustrated. Many hardware design houses use 15 FPGAs on a board for testing. The Xilinx Virtex-7HT FPGA has analog, memory, and ARM microprocessor integrated on a single chip giving a throughput of 2.8 Terabits/second. He also mentioned that Known Good Die (KGD) methodologies are still emerging in the market. For the last track of the conference, I attended the sessions on “C9. Advances in Circuit Simulation, Analysis and Design”.

Shakthi Kannan

Thanks to Red Hat for sponsoring me to attend the conference.

About the Author – Shakthi Kannan

Shakthi Kannan is a Senior Software Engineer with Red Hat in Pune, and is also a very active member of the open source community. For more details about him, see his Linkedin Profile, or his blog.

LiveBlog: Maharashtra CM Prithviraj Chavan’s address at VLSI Conf Pune

Live Blogging, , , ,

(This is a live-blog of the keynote address of Prithviraj Chavan, CM of Maharashtra, at the 26th International Conference on VLSI Design that is currently going on at the Hyatt, in Pune. For those who didn’t know, Prithviraj Chavan is an electrical engineer from BITS Pilani and Univ of California, Berkeley.)

The semiconductor industry in India started first in Bangalore, and then in Delhi/NCR. Pune is late to this game. But we have the potential to better than Delhi/NCR, and even Bangalore.

These are the things that need to happen for Pune to become a semiconductor hub:

  • Government should create facilities where the expensive EDA tools are setup, and various companies from industry can sign up for use of the tools.
  • Work on increasing the quality of manpower in and around Pune. We have to potential of having one of the highest ratios of high quality – low cost manpower. We need to work with universities and other educational institutions in this area.
  • We should continue trying to attract fabs to come and setup in Pune

We are a large customer of mobiles and other electronic devices. As we continue to grow at 8-9%, we will become an increasingly attractive market. And there will also be many opportunities to create specialized devices for local markets. This can drive innovation and incubation.

The CM said that he is completely committed to working with us (i.e. the tech community in Pune) to ensure that Pune gets put on the semiconductor map. He announced that any company investing in semiconductors in Maharashtra will get a rebate on their VAT until they recoup their investment. In addition, he hopes that the government will be able to help jumpstart this industry by these means:

  • Government will set up the physical infrastructure
  • Government will put up the initial funding for the expensive tools
  • Government will set up training facilities to get people started on this
  • We should together set up server farms, and other infrastructure needed to get started

Maharashtra is larger than most countries in the world, as large as Mexico, and larger than any European country. It attracts 33% of the FDI that came into the country. Maharashtra is well positioned to become the chip destination of India.

What NVidia is up to – NVidia Tech Week Open House in Pune

Event Report, Featured, ,

(This report of an demo/event organized by NVidia in February 2012 was written by Abhijit Athavale, and was originally published on PuneChips.com, a PuneTech sister organization that focuses on semiconductor, eda, embedded design and VLSI technology in Pune. It is reproduced here for the benefit for PuneTech readers.)

I was invited to visit the Nvidia Tech Week this past weekend (February 25-26, 2012) at their facilities in Pune. This is a great concept – getting employees to invite friends and relatives to actually see what their company is all about is very good social outreach and a fantastic marketing initiative. If more tech companies in the area do similar events once or twice a year, it will help lift the shroud of technical opaqueness around them. I think hosting similar events in area colleges will also help students realize that even VLSI/Embedded Systems Design is cool.

I was given a personal tour by Sandeep Sathe, a Sr. Development manager at Nvidia and also met with Jaya Panvalkar, Sr. Director and head of Pune facilities. There was enough to see and do at this event and unfortunately I was a bit short on time. It would have taken a good two hours for a complete walk-through, so I decided to spend more time on the GPU/HPC section though the Tegra based mobile device section was also quite impressive. It’s been a while since I actually installed a new graphics card in a desktop (actually, it’s been a while since I used a desktop), but graphics cards have come a long way! Nvidia is using standard PCI Express form factor cards for the GPU modules with on-board fans and DVI connectors.

The following are key takeaways from the demo stations I visited

GeForce Surround 2-D

Here, Nvidia basically stretches the game graphics from a single monitor to three monitors. Great for gamers as it gives a fantastic feel for peripheral vision. The game actually doesn’t have to support this. The graphics card takes care of it. The setup here is that while the gamer sits in front of the main monitor, he also sees parts of the game in his peripheral vision in two other monitors that are placed at an angle to the main monitor. I played a car rally game and the way roadside trees, objects moved from the main monitor to the peripheral vision monitors was quite fascinating.

GeForce 3-D Vision Surround

This is similar to the above, but with 3D. You can completely immerse yourself in the game. This sort of gaming setup is now forcing monitor manufacturers to develop monitors with ultra small bezel widths. I suppose at some point in the next few years, we will be able to seamlessly merge graphics from different monitors into one continuous collage without gaps.

Powerwall Premium Mosaic

Powerwall is a eight monitor setup driven by the Quadro professional graphics engine. Two Quadro modules fit into one Quadroplex industrial PC to drive four monitors. Projectors can also be used in place of monitors to create a seamless view. The display was absolutely clear and highly detailed. The Powerwall is application transparent. Additional coolness factor – persistence data is saved so you don’t lose the image during video refresh and buffer swaps. This is most certainly a tool intended for professionals who need high quality visuals and computing in their regular work. Examples are automotive, oil and gas, stock trading.

PhysX Engine

PhysX is a graphics engine that infuses real time physics into games or applications. It is intended to make objects in games or simulations move as they would in real life. To me this was very disruptive, and highlight of the show. You can read more about PhysX here. It is very clear how PhysX would change gaming. The game demo I watched had several outstanding effects: dried leaves moving away from the character as he walks through a corridor, glass breaking into millions of shards as it would in real life. Also running was a PhysX simulation demo that would allow researchers to actually calculate how objects would move in case of a flood. What was stunning was that the objects moved differently every time as they would in real life. PhysX runs on Quadro and Tesla GPUs. It is interesting to note that Ra.One special effects were done using PhysX.

3D photos and movies

Next couple of demos demonstrated 3D TV and photo technology using Sony TVs and a set of desktops/laptops. Notably, the Sony 3D glasses were much more comfortable compared to others. Nvidia is working with manufacturers to create more comfortable glasses. There was also a Toshiba laptop that uses a tracking eye camera to display a 3D image to the viewer regardless of seating position without glasses. It was interesting. However, the whole 3D landscape need a lot of work from the industry before it can become mainstream.

Optimus

What was explained to me was that Optimus allows laptops to shut off GPUs when they are not needed. They can be woken up when high performance work is required. This would be automatic and seamless, similar to how power delivery is in on a Toyota Prius. This sort of a technology is not new to computing – a laptop typically puts a lot of components to sleep/hibernate when not being used, but the GPU is not included.

Quadro Visualizations

This allows 2D/3D visualizations for automotive, architectural and similarly complex systems for up to one thousand users at a time. You can easily change colors, textures, views so everyone can comment and give constructive feedback. I was not sure if the design can be changed on the fly as well. Nvidia is working with ISVs like Maya and Autodesk on this.

Tesla

Tesla GPUs use chips that are used for high performance computing and not rendering, which is different from what Nvidia typically does. The Tesla modules do not have any video ports! It has a heterogeneous GPU/CPU architecture that saves power. In fact, the SAGA-220 supercomputer, dubbed India’s fastest, at ISRO’s Vikram Sarabhai Space Center facility uses 2070 Tesla GPUs along with 400 Intel Xeon processors. In addition to supercomputing, Tesla is very useful in 3D robotic surgery, 3D ultrasound, molecular dynamics, oil and gas, weather forecasting and many more applications.

Tegra Mobile Processor

Next few demos showcased the Tegra mobile applications processor based on ARM Cortex A9 cores. The HD quality graphics and imaging were impressive. It is clear that smartphones and tablets of the day are clearly far more powerful compared to desktops of yesteryear and can support highly impressive video and audio in a very handy form factor.

In all, I had a great time. As I mentioned earlier, Nvidia along with other tech companies in Pune should hold more of these kinds of events to give technology exposure to the larger population in general. I think it is important for people to know that the stuff that makes Facebook run is the real key and that is where the coolness is.

Profile: Renu Electronics & Ajay Bhagwat

Featured, Interview, , ,

(This article is a based on a broad and free-wheeling interview of Ajay Bhagwat, founder of Renu Electronics, by Navin Kabra and Amit Paranjape)

To a large extent, the computer technology in India is synonymous with software technology. So, when we found that Renu Electronics manufactures all its own hardware for all the products it sells, including LCD panels, and that this is all being done in a small building on Baner Road, we were shocked.

Renu Electronics, founded by Ajay Bhagwat, has generally maintained a low profile, but has a very interesting story to tell.

Early Years

Ajay has an interesting educational background. After his engineering at IIT-Bombay, he went to the US on an L&T scholarship, and did his Masters from the University of Iowa. Here, he excelled, finishing his Masters in 9 months, in the process getting some really interesting results. Specifically, he figured out an algorithm in control systems to determine whether a particular system’s transfer function could be identified adaptively or not. This result was useful enough that some senior professors from UIUC and industry folks from GM requested him to do some additional work on this algorithm to get some specific results they were interested in. For this additional work, which he did in a few months, he got an one more Masters degree from University of Illinois at Urbana-Champagne.

1990s – Starting Renu Electronics

Ajay came back to Pune in 88, and by 1992, had decided to start Renu Electronics, 100% export oriented unit selling HMIs (human machine interfaces; i.e. front end control panels for industrial control systems). The basic idea was to sell a common front end panel that could talk to many different backends and give the customer a common interface. The trick is to be able to talk all the different protocols of the different backend systems (which did not have standards or interoperability). This was done using a core firmware and then pluggable drivers for each backend – which also made it easy to add support for new backends. This was a big improvement in usability since having to teach floor technicians a different front end interface for each backend manufacturer was a major pain point for his customers.

At this time, the majority of the business came from white labeling this technology to established brands. Even GE approached them and started selling this technology under the GE brand. He was one of the few people in India at that time who was exporting technology to the US and Europe instead of importing it. When he was filling out a customs department form for this purpose, he got scolded by the customs officer for putting machinery in the outgoing column and money in the incoming column. The officer knew that things are supposed to be the other way around. It took a long time to convince him that the form was indeed correct.

Building Products

Renu’s flagship products are HMIs which allow industry floor operators to do configuration entry, monitoring of status, alarms in case of exceptional conditions, production of reports, and trends (graphs).

By 1995, Renu had decided that they would manufacture all their own hardware. By designing the entire system in-house they were able to achieve efficiencies that wouldn’t have been possible otherwise. For example, they used the 8051 chip, and made maximal use of all the features of this chip, so that they were able to do alarm handling, interfaces, dual-port communications, using just the internal RAM of the 8051 chip – which is just 256 bytes. This gave them a huge cost advantage. At one time, they got threatened by a competitor from Europe that dumping (i.e. selling a product at a price less than it costs to manufacture) is illegal and they would take action. The competitor was very surprised to learn that Renu was actually making a 20% profit in spite of the ridiculously low price.

Renu have always been a product company. They have never done a custom product for anyone, and they’ve always owned their own IP.

Initially, they were only providing the front ends, but soon they wondered whether they they should make their own PLC. All the top PLC companies were Renu’s customers, and Renu did not want to upset the customers. But it turns out that customers actually encouraged Renu to enter this space. They were not worried about competition from Renu, but were happy that Renu would understand the market and domain even better and come up with even more innovative products that they could white label.

Renu was the first company in the world to put the PLC in the HMI itself. This works well for smaller systems. But it also led to too many different products and was messy in terms of sales and marketing – and was confusing to customers. So they designed a modular system which allows PLCs to be chained together to create simple or complex PLCs depending upon what exactly the customer needs. This makes it easier for the customer to create a customized system that exactly meets their needs, without having to go for a high-end, expensive system. The fact that the HMI can be with the PLC, and there is no new system and software to be integrated and learnt is another advantage. Now, finally, they have started a line of modular PLCs without the HMI, and most growth in recent years is coming from
the modular PLCs (with or without HMIs).

Focus on Quality

One of the biggest problems faced by Ajay was that neither he (nor most other people in India) understood how to create an industrially robust process. This resulted in manufacture of components that had latent problems – i.e. units that work perfectly fine, but stop working 6 months later. After they continued to have latent failures they learnt from their customers the various things they need to do to ensure long-term quality of their devices. They spent lots of time and money getting in-house quality control equipment and processes. This high level of quality control results in very reliable products – and this is now one of the USPs of Renu Electronics.

We took a tour of the premises and saw some of the advanced equipment used for testing at Renu. There’s one unit that allows devices to be tested at temperatures from -40 to +60 degrees Celsius. Another unit allows humidity testing up to 98% humidity. A voltage fluctuation/spike/pulse tester can produce a spike of 2Kv in 1 nanosecond. This is in addition to vibration testers, RF interference testers, and 60+ other tests. They have installed anti-static flooring on their manufacturing area. This is very expensive at Rs. 1600 per square foot, but has paid off handsomely, because their latent errors are now down to almost zero.

Staying Ahead of The Curve

Renu believes in implementing processes that they believe are the right thing to do in the long term irrespective of whether they are immediately required by customers or the law. For example, Renu is one of the few ISO-14001 compliant companies. Sometimes, this causes a problem for other companies, because Renu sets the standard and soon the others are expected to follow. On the other hand, sometimes this causes a problem for Renu.

For example, Renu was one of the first companies companies that was ROHS compliant. For this, they had to invest in ROHS compliant machinery and components – which cost significantly more. Further, their running costs went up, because the components they needed on a regular basis were more expensive. But, they’re still ROHS compliant because it is the right thing to do. This story has a happy ending (financially) though – from 1st January, 2012, this investment is going to pay off because there are two new Indian Government directives that will enforce control of hazardous materials, and Renu will already be compliant, whereas other companies would have to struggle.

KPIT Story

Ajay Bhagwat was also one of the promoters of KPIT, one of Pune’s most well known software services companies.

When Ajay was in IIT, he was very interested in music, and would organize and compete in music competitions (he was one of the people behind the creation of a program called Sur-Bahar, which still happens). Shirish Patwardhan was one of the people Ajay used to bump into at music competitions at IIT. Later, in the late 80s they met again in Pune, and started talking about starting a company for doing software products/services. So Ajay joined the software wing of Kirtane and Pandit (an accounting firm) and KPIT was born. Ajay helped set up the quality systems, and the embedded team for KPIT. Although Ajay has been out of day-to-day functioning of KPIT for a long time, he was a director of KPIT until recently.

Contributions to the tech/startup ecosystem in Pune

To those watching the startup ecosystem in Pune, it is clear that Ajay is also one of people helping TiE Pune’s revival this year. This year, TiE has had fortnightly ‘My Story’ sessions with very interesting and accomplished entrepreneurs, and monthly ‘Breakfast sessions’ with more free-wheeling discussions on issues of interest to entrepreneurs. This vitality of TiE in Pune is a very welcome addition to the startup ecosystem in Pune, and will certainly go a long way in cementing Pune’s position as one of the top destinations for doing startups in India.

As a charter member of TiE Pune, Ajay also sets aside 5 to 6 hours every week for one-on-one mentoring of entrepreneurs in Pune. This is a non-trivial time-commitment for any busy executive, but even that, says Ajay, is not enough. There is need for more mentorship of entrepreneurs in Pune. If you have a startup in Pune with actual revenues and enterprise sales, we would suggest talking to Ajay
for some guidance.

PuneChips Event: PCI Express Architecture and Applications for FPGAs – July 30

External Visitors, ,

PuneChips invites everybody to a talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik, a Principal Architect at Xilinx. This talk will be on 30 July, 10:30am, at the Venture Center, NCL Innovation Park, Pashan Road.

Abstract

Modern FPGA devices offer great advantages for designers of industrial imaging, networking, automation and control, data acquisition systems for test, industrial and medical applications. Apart from offering high performance programmable fabric, FPGAs offer a wide variety of IO standards to interface with networks, motors, sensors, transducers, offer built in high density data storage and the ability to interface to high speed external memory devices. But, most importantly FPGAs offer Gigabit serial connectivity via standards based protocols such as PCI ExpressTM. The ubiquitous nature of PCI Express technology enables development of FPGA based plug and play board and card products that interface with standard off-the-shelf embedded compute and communications platforms, running WindowsTM, Linux or other operating systems and custom device drivers. PCI Express 3.0 Architecture offers many reliability, availability and scalability features to address application needs, as well as advanced features such as relaxed transaction ordering, transaction processing hints, optimized buffer flush-fill, active power management to achieve the highest throughput performance possible within the platform’s power and thermal budgets.

About the speaker: Kiran Puranik

Kiran is a Principal Architect at Xilinx, Inc., responsible for serial connectivity protocol products such as PCI Express. He has spent the last 10 years at Xilinx engaged in architecture definition, design, development and verification of Intellectual Property blocks for several generations of FPGAs. Before Xilinx, Kiran held various engineering positions in the field of ASIC, ASSP design and ICCAD software development.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. It was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start & grow their businesses.

Please forward this information to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

Fees and Registration

This event is free and open for anybody to attend. No registration required.

PuneChips Event: Building an Autonomous and Scalable Semiconductor VLSI Business

Events, ,

PuneChips, the forum for everybody interested VLSI, semiconductor and embedded technologies in Pune, along with LSI Corporation invite you to a talk on Building an Autonomous and Scalable Semiconductor VLSI Business. This talk is by Dr. T.R. Ramachandra, a Senior Director in the Storage Peripherals division of LSI.

The talk is on Wednesdah, 13 July, from 9:30am to 11am at LSI’s office near the airport.

Abstract: Building an Autonomous and Scalable Semiconductor VLSI Business

The presentation focuses on effective ways to build autonomous and scalable semiconductor VLSI businesses. The trends in the VLSI industry and inherent challenges of growth make autonomy & scale-building essential elements of long-term success. This is particularly relevant to emerging geographies like India where there is increased focus on enhancing end-to-end capabilities and overall management.

About the Speaker – Dr. T.R. Ramachandran

T. R. Ramachandran is Senior Director for Product Operations in the Storage Peripherals Division at LSI. In this role, he reports to the Senior Vice President and General Manager of the division and is responsible for the operations infrastructure, business processes, IP and customer program management across the entire product lifecycle from planning through manufacturing ramp for LSI’s highest volume semiconductor business. Before assuming this role, TR held a number of positions in LSI where he brought to bear a unique blend of expertise in a range of areas from business, operations & program management, strategic/competitive analysis, large-scale M&A and business transformations, global product development and deployment, and supplier & manufacturing management. He lives in the United States in Northern California, and is keenly interested in various aspects of technology & broader public policy as well as problems of scale tied to private, public and/or non-governmental sectors.

TR received a Bachelor’s degree in Metallurgical Engineering from IIT-M (Indian Institute of Technology in Madras/Chennai) and is a recipient of the Dr. Dhandapani Prize from IIT-M and the Vidya Bharati Prize conferred by the Indian Institute of Metals. He received his Masters and Ph.D. degrees in Materials Science from the University of Southern California, Los Angeles. His Ph.D. was focused on structural and optical studies of semiconductor thin films & quantum dot nanostructures and innovative forays into nanotechnology using scanning probe microscopes.

About Pune Chips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

For more information, see the PuneChips website, and/or join the PuneChips mailing list. Please forward to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

Fees and registration

This event is free and open for anybody to attend. RSVP Reshma Arthani: Reshma.Artani@lsi.com, Mobile: +91.992.320.3557

The talk is at: Sargam Auditorium, 4th floor, LSI India, Commerzone, Samrat Ashok Path, Off Airport Road. Wednesday 13 July, 9:30am.

PuneChips Event: Advanced System Verilog Tips with Cliff Cummings – 19th April

External Visitors, Featured, ,

Abhijit Athavale writes:

SystemVerilog Guru Cliff Cummings is back in town and he will be holding another seminar on April 19th at MCCIA’s Sumant Moolgaokar Auditorium, ICC Towers, Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to re-engage with him.

The topics covered will include:

  • New UVM 1.0 overview and comparison to OVM
  • Important OVM and UVM phasing
  • Secrets in mastering OVM and UVM
  • Graceful termination of tests in OVM and UVM with emphasis on the objection mechanism
  • Some of Cliff’s favorite SystemVerilog tips and tricks
  • Some early UVM techniques and best practices

This event is co-sponsored by Qlogic and Cadence who I must thank profusely on behalf of the PuneChips community. It is not very often that internationally renowned experts visit our city and hold free seminars, but QLogic and Cadence have made it possible. So, I encourage everyone who has any interest in SystemVerilog to attend and participate.

This event is completely free, but registration is required. Please visit this link to register and view the agenda.

PuneChips Event: An Overview of RFID – 16 April

Events, , ,

PuneChips, the community for all those interested in semiconductor design and applications presents an Overview of RFID by Ashim Patil, on 16th April, at Venture Center, NCL, Pashan Road, from 10:30am to 12-noon.

Abstract of the talk – Radio Frequency Identification

Product, people and document identification is now a huge challenge. Radio Frequency Identification (RFID) offers an active ID mechanism that requires no intervention on the part of the user. This presentation will introduce the RFID technology, positioning and its variants. The speaker will also introduce Near Field Communication (NFC) and its differences with regular RFID. RFID and NFC applications across several verticals in India will also be discussed.

About the speaker – Ashim Patil

Mr. Ashim A Patil is the MD & CEO of Infotek Software & Systems Pvt Ltd., also known as i-TEK. Under his leadership i-TEK is one of the leading RFID (Radio Frequency Identification) system integration companies in India. i-TEK has several live RFID sites across verticals like Manufacturing, Banking, Education and Healthcare. i-TEK has to its credit RFID applications like File & Document Tracking, Asset Management, Stores Management, Automatic Vehicle Identification, HNI Tracking and many more, deployed at leading organisations in India.

Mr. Patil has completed his engineering degree from University of Pune in 1998. Fresh out of college, he began his entrepreneurial journey starting an Aptech franchisee which he sold in 3 yrs. After that, he took over an ailing software company in Pune which later on became today’s successful i-TEK under his able guidance. He shifted the focus to RFID when not many were even aware what the acronym stands for.

About Venture Center

Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

For more information, see the PuneChips website at http://punechips.com, and/or join the PuneChips mailing list: http://groups.google.com/group/punechips. Please forward this mail to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

Fees and registration

This event is free and open for anybody to attend. No registration required.

Materials, mechanics, thermals, speed, power – Overview of Integrated Circuit Packaging – PuneChips 10th July

Events, punechips, , , ,

What: Overview of the field of electronics packaging – by Dr. Sandeep Sane, Intel Corp, (Ph.D. CalTech)
When: Saturday, 10 July, 10:30am to 12:30pm
Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture Center on the right hand side. Map
Registration and fees: This event is free for all to attend. No registration required.

PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips
PuneChips is a PuneTech special interest group on semiconductors, VLSI, embedded, and EDA. Click on the Logo to see all PuneTech articles about PuneChips

Electronic Packaging – Materials and Mechanics Challenges

Electronic packaging has typically been defined as providing an enabling function and a space transformer between the IC feature sizes and the board & system level interconnects and over years it has grown to become a ubiquitous part of the overall electronic assembly. In certain market segments, such as flash memories, the package has evolved to become a key product differentiator and performance enabler. The scope of electronic packaging is very broad across multiple application areas such as CPUâs and Chipsets for the desktop, mobile and server segments, hand-held and wireless devices, telecom components & network processors, and memory devices; with each segment potentially having its unique set of demands and constraints such as the form factor, function, cost, reliability requirements, thermal and electrical performance.

To ensure that right technical and cost-effective solutions are defined, developed and deployed across the different market segments, electronic packaging provides significant research and development challenges and opportunities across multiple disciplines including materials, mechanics, reliability, thermals, high speed interconnects, power delivery and manufacturing.

This presentation will first provide an overview of current and future package technologies and associated demands in the different market segments, followed by focusing on some of the recent progress made in addressing some of the mechanics and materials challenges and highlight opportunities in future packaging technology development.

About the speaker – Dr. Sandeep Sane

Sandeep Sane received his Ph.D. from California Institute of Technology, Pasadena in Aerospace Engineering with major in Solid Mechanics. He holds M.S. in Aeronautics, California Institute of Technology and B.Tech in Mechanical Engineering from Indian Institute of Technology, Bombay (Mumbai).

Sandeep is currently a Technology Development manager in the Assembly and Test Technology Development (ATTD) organization, Intel Corp., Chandler. He manages a technical team of 30 engineers including an experimental mechanics laboratory; equipped with start of art analysis and validation metrologies. His team is chartered to deliver fundamental understanding of various mechanical issues in electronic packaging, establish roadmaps for ATTD and work directly with Intelâs customers (OEM/ODMs) and suppliers to resolve mechanical issues. He is also responsible for delivering novel mechanical analysis, material characterization and validation techniques to help optimize design, material and process changes to deliver reliable and cost effective solutions for Intelâs packaging technologies. Sandeep has led and participated in numerous taskforces and management review boards to resolve critical issues in a timely manner impacting Intelâs bottom-line. Prior to joining Intel, he was a Development Staff Engineer with IBM, Endicott, NY, working in Mechanical & Thermal Analysis group.

Sandeep has filed for more than 15 patents and have published several technical articles in various conferences and journal proceedings. He is also a recipient of numerous awards across Intel for his technical contributions. He is a member of ASME, IEEE and an active member of organizing committees for ASME and IEEE conferences. He also serves on Industrial Advisory Board for Mechanical Engineering at University of Colorado, Boulder and NSF review committee.

About Venture Center

Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips

PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

PuneChips has been started by Abhijit Athavale, president and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at several companies. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

For more information, see the PuneTech wiki profile of PuneChips, and/or join the PuneChips mailing list.

Please forward this mail to anybody in Pune who is interested in semiconductors, chip design, VLSI design, chip testing, and embedded applications.