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Archive for the ‘EDA’ tag.

Introducing http://PuneChips.com: The PuneTech SIG on Semiconductors, EDA, VLSI, Embedded Systems

Over the past 2 years, PuneTech has covered a breadth of technology related topics, with a concentration on Information Technology & Software. The strategic goal is to cover multiple technology segments and discuss innovative & exciting developments in these areas; specifically in Pune’s context. It was with this objective that the concept of ‘SIG’ (Special […]

PuneChips Editor’s Blog – SystemVerilog and Designer Productivity

As chip design complexity increases, designer productivity is failing to keep up. Industry must innovate and provide design tools that address this problem to survive and prosper.

PuneChips: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL tricks for Design Engineers – 5 Nov

What: Talk by Cliff Cummings on SystemVerilog FSM, Assertion, & RTL Tricks for Design Engineers When: Thursday, 5th November, 6:30pm to 8:00pm Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation Park / Venture […]

CORRECTION: ASIC Verification – guest post by Arati Halbe

Yesterday’s PuneTech post, “ASIC Verification: Trends and Challenges” was actually a guest post by Arati Halbe. Due to an oversight, I forgot to include the “About the Author” section in the post (in fact, I forgot to include any mention of the fact that the post was by Arati.) I apologize for the oversight. Arati […]

ASIC Verification: Trends and Challenges

(This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune […]

PuneChips Event: ASIC Verification trends and challenges – Jagdish Doma, former director of VLSI design Conexant Systems – 20 Aug

Image via Wikipedia What: Trends and Challenges by Jagdish Doma, former director of VLSI design for Conexant Systems When: Thursday, 20th August, 6:30pm to 8:00pm Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll find NCL Innovation […]

Too Soon to call for a Semiconductor Recovery?

Is it too soon to call for a semiconductor recovery? Market pundits are calling a semi bottom and some are expecting a surge in second half of this year. Is that really going to happen? Read more to find out …

PuneChips Editor’s Blog – Second Edition

First, an update on PuneChips – we now have 5465 members in the Linked In group and over 40 in the Google Groups mailing list. Some folks doing applications work have also joined us. Given that there are 300 or so semiconductor designers in the Pune area, and hundreds more developing applications, we have ways […]

How green will be my valley?

The “greening” of all things commercial and industrial is all around us. Every industry from transportation to technology to power to finance is in a rush to be perceived as “green”. So should the EDA industry stay behind? Chaitanya Rajguru thinks not, and gives his thoughts on some possible scenarios on what may happen.

Event: IC Design Challenges in the Telecom sector – Shrinath Keskar, ex-MD Ikanos, India – 29th June

Image via Wikipedia What: Talk by Shrinath Keskar, fomer MD Ikanos Communications India, on IC Design Challenges in the Telecom Sector. When: Monday, 29th June, 6:30pm to 8:00pm Where: Venture Center, NCL Innovation Park, Pashan Road. To reach Venture Center, go past NCL towards Pashan, pass the cricket ground adjacent to NCL and then you’ll […]